Scalable Atomicity

KC705 Supported

2012-01-29T06:49:00.000-08:00

With the release this month of ISE 13.4, we have added the Xilinx KC705 to the list of supported OpenCPI FPGA platforms. We adapted the new AXI-centric Gen2 x4/x8 PCIe endpoint to our uNoC without much drama. Inbound (RX) straddled packets were an interesting twist. Kudos to the Xilinx team for producing such a clean and easy-to-use evaluation kit and help jumpstart our community adoption of 28nm FPGAs in practice. The KC705 is fitted with a Xilinx Kintex-7 XC7K325T device.

KC705 at Atomic Rules

North American FPGA Conferences

2011-12-01T14:32:00.000-08:00

Atomic Rules is pleased to be a sponsor of two FPGA conferences in 2012:

FPGA-2012 in Monterey (ACM/SIGDA)
FCCM-2012 in Toronto (IEEE)

Please click through the links above to get the details on the call-for-papers and other participation.
Additionally, you can check our News and Events page to see what else is in the works.

Shep and Oskar at Demo night, FCCM-2005 (Napa)

SIGINT bliss and the MDO4104

2011-11-28T07:17:00.000-08:00

Regrettably we will part today with the Tektronix MDO4104-3 mixed-domain scope which we have been renting for two months. This is has been a superb instrument to use to line up RF and baseband signals. We hope to see this tool on our bench again soon.

Tektronix MDO4104-3 at Atomic Rules

FPGA Cross-Vendor Interoperability

2011-08-31T07:15:00.000-07:00

A short video showing OpenCPI transport messages between Altera and Xilinx FPGA platforms.

Pure PCIe

2011-08-16T17:44:00.000-07:00

The PCIe specification does a splendid job of describing how Transaction Level Packets (TLPs) are encoded. The specification precisely defines an interface without dictating an implementation. It’s a terrific concept.

FPGA and ASIC IP vendors, when providing said TLP interfaces to their users, make implementation choices that are specific to their own technological and marketing whims. These choices run the gamut from reasonable to ridiculous: Big-endian vs. Little-endian? Streaming or not? Header vs. Payload? Strict or Uncertain flow-control.? Packing “bubbles” and straddled packets? My goodness: All of these to alter of protocol gods that have little to do with PCIe TLPs themsleves!

Faced with the challenge of achieving interoperability with and between any of these PCIe endpoints; out of necessity, we followed a simple process. We designed a Pure PCIe intermediate “platform” that used nothing other than the “pure” PCIe specification for its definition. In this way, the work involved with adapting any PCIe device (now or future) has one overarching goal: Adapt the variable implementation to the fixed, pure PCIe interface.

The utility of this simple approach is that interconverting between different implementations is now just a matter of hooking them to the other side of the pure PCIe interface. We get multiplicative gains in interoperability for a linear effort in design cost. And we get the verification leverage of only having to compare one unknown (the new protocol) to one bulletproof interface (the PCIe TLP spec) at a time.

The lesson here is that there are indeed clever tactics one can take to embrace the reality that new protocols (some brilliant, some defective) will continue to assault us as they are invented. By recognizing stable, more cardinal interfaces (such as PCIe TLPs), we can adopt them all, without as much drama and cost.

Validating PCIe

2011-05-31T05:31:00.000-07:00

LeCroy graciously loaned us their exceptional T2-16 PCIe Protocol Analyzer for a few days. This was not nearly enough time to appreciate an instrument that has such deep capabilities. While the T2-16 captures every nook and cranny of the PHY and LINK layers; we remain most-interested in watching what is going on at the Transaction Layer (TL). The T2-16 does this well; but a Ferrari can also take you to the grocery store. Functionally, the most-annoying nit was that the fans on the active interposer and in the chassis itself are screaming loud. And the LAN function didn't work; but USB worked flawlessly. Faced with an intractable, hard-to-understand PCIe issue; this is an instrument we would want by our side.

LeCroy T2-16

FCCM 2011

2011-05-04T05:48:00.000-07:00

FCCM 2011 was a success. Good papers, excellent presentations, and a demo night.

Images from FCCM 2011

FCCM 2011 Arrival

2011-05-01T05:25:00.000-07:00

Salt Lake City is pretty. The last time I was here, we were we're hashing out the details of the FMC Standard up in Park City. This time it's FCCM. Dinner last night at Fresco was delicious.

FPGA Design Intern Position

2011-04-28T05:36:00.000-07:00

Job Title: FPGA Design Intern

Location: Auburn, NH

Stipend: $20/hour

Dates of Position: Flexible

Time Commitment: 3 to 6 months

Reporting To: CTO

Responsibilities: Design, simulation, and test of digital infrastructures and applications. The intern will write, test, and deploy BSV codes that will be contributed to an open-source community.

Qualifications:

Bluespec SystemVerilog (BSV) experience (MIT 6.375 or equivalent) (mandatory)
Experience with FPGA design and tool flows from Verilog sources (mandatory)
Familiarity with RHEL, C, C++, Tcl, Python, Git and MATLAB
Familiarity with OSS projects like www.opencpi.org and www.netfpga.org

Additional Details:

The intern may work remotely
This position is non-ITAR; no clearance or US citizenship is required
Atomic Rules builds heterogeneous circuits and systems centered on leading-edge FPGAs. We seek qualified, enthusiastic intern contributors.

Contact greatminds at atomicrules dot com

Ubiquitious 10GbE

2011-03-09T03:52:00.000-08:00

Five months after our travels to Dublin we have the NetFPGA-10G "NF10" board lit up and shuttling data across 10GbE and PCIe. There's no looking back, 10GbE is here.

NF10 in Core980 with ML605

It's About Time

2010-11-28T09:05:00.000-08:00

We care about time. An ongoing effort is to improve the quality of timestamp available to IP cores inside an FPGA to sub-nanosecond precision. One way forward is to use a stable, but not terribly accurate, on-board XO; and then to discipline it to a highly-accurate, but transient, reference from a GPS. Our approach uses a PI servo that is smart about when to freewheel. No magic. Just math.

Agilent 53230A 20pS Counter/Timer

Narcissism of Small Differences

2010-11-13T03:53:00.000-08:00

One of Seth's posts, as it often does, got me thinking.

emacs vs vi
VHDL vs Verilog
AXI vs OCP

The good news is that we care. I was going to add "Functional vs Imperative", then reflected, not such a small difference.

NetFPGA-10G and OpenCPI

2010-11-13T03:35:00.000-08:00

Xilinx ran an article in their "Xcell Journal" describing NetFPGA-10G and the supporting role of OpenCPI.

At Xilinx Research Labs (Dublin)

10Gb Ethernet

2010-10-22T04:52:00.000-07:00

We've been fortunate to have the opportunity to contribute to the NetFPGA-10Gb effort some of our expertise in PCIe DMA. Just back from a few days in Dublin sorting out the twisty bits. A great team!

PCIe DMA (October-2010)

Abstract and Concrete

2010-08-24T06:18:00.000-07:00

There's no doubt that Hardware/Software co-design is a popular and challenging topic. In the embedded world, there is an added twist that real world voltage potentials exist and currents flow, as a result of the hardware and software. It's a system! Throughput, Latency, and Power that you can actually measure unambiguously!
We find it grounding to put drafty concepts on simple footings.

AR RF Bench (August-2010)

OCP and AXI

2010-06-18T03:14:00.000-07:00

OCP and AXI seem a lot like Coke and Pepsi. RTL interface specifications and refreshing cola beverages. The choice of one or another does not matter at a certain level of abstraction. As an application-domain specifier, you may not care very much: "I'd like a stream interface please". Of course, the particular dining establishment you are visiting may respond to you "Oh, we don't have Coke, is Pepsi OK?"
This seems to have worked out well, at least with the cola beverage thing. And we are hoping the same will play out with OCP and AXI. Some establishments will have a predilection for one or the other. That's fine. Both OCP and AXI can provide interface patterns suitable for control, streaming, and messaging. We've abstracted these patterns in OpenCPI's Worker Interface Profiles. These interface patterns for RTL are like classic, diet and caffeine-free for cola.

Sometimes work allows some laughs (FCCM-2010)

The Correct Abstraction

2010-05-12T17:06:00.001-07:00

The science and math behind the business of engineering is terrific. There is often a spectrum of choice for a particular implementation. That hardware and software can be abstracted in a similar fashion is hugely empowering. More choice! But we need metrics, hard quantitative measures to validate our decisions. Otherwise it's just qualitative balance.

4DSP FMC Card (2010)

ADO Firmware (1981)

Preparing for FCCM Charlotte

2010-04-26T03:54:00.000-07:00

FCCM-2010 is in Charlotte in a week. There is a lot to prepare.

Napa has wine, what will Charlotte offer?

Well Connected

2010-03-06T06:26:00.000-08:00

Validating performance of ADCs and DACs is hard enough for the converter and board vendors. We have those challenges, as well as system level concerns. When you place an converter a few cm from a 100W GPU, how would you think the SFDR would change? Fun stuff.

GPU and FPGA Love

Big DAC Attack

2010-01-24T11:59:00.000-08:00

We've been putting some miles on the amazing RF ADCs and DACs that are now available. In particular, we like the Maxim MAX19693, a 4GSPS 12b DAC that is exceptionally well-targeted at our market's needs.

RF Bow-Tie

A Brief History of FMC (VITA-57)

2009-12-13T06:53:00.000-08:00

The FPGA Mezzanine Connector (FMC) standard is just starting to become popular. It's said to be "brand new". However work on the concept and specification began in 2005 when FPGA vendors and clients realized that specializing IO for FPGA was a serious challenge. My speculation was that the idea was born in a dialog between David Squires and Craig Lund. They passed the concept along to their respective underlings Sabine Lam and me. On November 16, 2005 over two dozen industry participants came together at the Paramount hotel in Seattle, WA to hash out a standards development roadmap. The team promptly put Malachy Devlin (then CTO and co-founder Nallatech) in the lead role. Throughout 2006 there would be face-face meetings in Monterey, Park City, and Madrid, to work through details not covered in the weekly con-calls. By the end of 2007, the "VITA-57" had become "FMC" (after "XMC", "AMC", etc), and the standard was out for approval. In 2008, VITA placed the documents on their FMC web page. And in 2009 we see the first flush of mezzanines and carriers hitting the market. A lot of work by a broad team to achieve consensus.

Park City, UT

Madrid

Monterey

ISE 11.4 L.68 Looking Great

2009-12-09T10:36:00.001-08:00

Like the first winter storm of the season outside our offices, ISE 11.4 L.68 rolled in last night. No issues through our first round of regressions with the OpenCPI oc1001-ml555 baseline. Vendors should follow Xilinx' lead for low-impact, minimally-disruptive minor releases like this.

1500 MHz DAC Pilot Tone

V6 - for real this time

2009-11-15T14:26:00.000-08:00

We've seen V6 teasers for months now. But it all became real when Avnet (our distributor) delivered V6-LX240T production silicon on ML605s last week. Fortunately, a rainy November weekend meant full steam ahead. I suppose we were expecting more problems. Essentially, everything works. Nice work, team X! Who's next?

More Boards, Less Risk

2009-10-25T09:03:00.000-07:00

This morning we successfully ran the the rplTest regressions on an OpenCPI corei7 reference platform with the Xilinx XUPV5-LX110T board. This bench test involved both passive and active DMA roles, host/fpga and fpga/fpga. The tests included swapping out one of two ML555s for an XUPV5; as well as testing the XUPV5 interacting with the GPP alone.

No Code changes were required to achieve this goal!

For the XUPV5-LX110T, we directed the make target in NGDBUILD to link against a Gen1-x1 NGC core (instead of Gen1-x8 core we use with the ML555), and of course, to use the XUPV5-LX110T UCF. Other than the expected, reduced DMA throughput seen with the Gen1-x1 PCIe link, we observed no functional differences. The bitstream build process for the reference oc1001 application took about 35 minutes.

ML555 and XUPV5

Silicon Valley Scramble

2009-09-19T08:40:00.000-07:00

We made a go of Silicon Valley this week, visiting academic, EDA and FPGA luminaries of past, present and future. This expedition found us relentless in replaying our OpenCPI message, with our audience actually comprehending the merits of our work. Reconfigurable Computing (RC) is indeed hard. But the values are real and can be measured against the costs. I'm eager to get back to the lab and playout the assets our hosts desire. Eager so that they can measure them, exploit them, critique them, and thus help steer our future.

More ML605 Love

2009-09-13T16:48:00.000-07:00

We got our hands on a real ML605 with ES1 silicon for a few days. Real harmony of tools, silicon, and etch. Have to give the loaner back tomorrow. But production boards are around the corner.

Sweet 40nm Fun

FPL 2009 Prague

2009-09-03T05:34:00.000-07:00

By all accounts, FPL 2009 in Prague was a success. We were especially excited about the interest in Open-Source for FPGA; both the opportunities and challenges. Fully expect reverberations in this regard to influence FPGA 2010 and FCCM 2010.

High Technology

Steve, Vaughn and Kati at Mustek

Control Plane Grows Up

2009-08-08T02:38:00.001-07:00

With the first drop of code out on the OpenCPI website we are doing some cleanup and feature-creep. We decided that the control plane should be able to swallow anything thrown at it; not just well formed 32b and 64b transfers.

An OpenCPI FPGA Hierarchy

ISE 11.2 L.46 Looking Great

2009-06-25T11:52:00.000-07:00

We've been having fun with beta versions of the backend tools from our FPGA vendors. Yesterday, ISE 11.2 L.46 went live, bringing V6/S6 builds into the non-NDA public eye. From our V5 ML555 viewpoint, things look great indeed.

OpenCPI Goes Live

2009-06-21T07:00:00.001-07:00

We moved closer to our goal of providing a vendor- and substrate-agnostic application container as the OpenCPI website went live last week. Much more on this in the months ahead.

OpenCPI Development - Spring 2009

V6 Functional on ML605

2009-04-30T05:19:00.000-07:00

We witnessed a demo of functional Xilinx V6 Silicon yesterday on their ML605 evaluation board. The Serdes was functional and operating at the 5 GHz needed for Gen2 PCIe. The two connectors on top are the VITA-57/FMC connectors.

ML-605 V6 Eval Board

FCCM 2009

2009-04-12T08:16:00.000-07:00

FCCM 2009 was a worthwhile endeavor and success.

The Usual Suspects

Words Matter

2009-04-01T16:48:00.000-07:00

Back in 2008 I read an awful, uninformed post on what I had thought to be a helpful and fair technology blog. I took the bait, and wrote a seven paragraph missive in response. Three months later, my response was posted; but it was severely diluted by the editor. While I'm glad my voice was heard, even as a squeak; my truths presented were castrated without any consent. The doc linked below is unedited:
Ref: S.Siegel, 2008-12-26, Letter to John Cooley

FPGA 2009

2009-02-26T10:25:00.001-08:00

As Rodger Daltrey exclaims, "The Kids Are Alright". And so too was FPGA 2009. There is more promise than ever. And it really isn't that tough to do better than RTL!

Shep Explains Bluespec SystemVerilog

Don't Forget the Solder Wick

2009-02-02T16:09:00.000-08:00

Our family has a nine year old CRT projector TV, one of the first consumer models that could scan 1080i. It lost red convergence a week ago, and I went a hunting for the fault. I was whining about yanking out the 18 pin power op amp that drives the red sub-coil yoke. Phil provided some motivation. Not just in his default "You are being a Wuss" cheer; but in the observation that there was little downside if I screwed up! That was all I needed to hear. An hour before kickoff, and we were good to go.

IC8C01

X58 Love

2009-01-11T14:45:00.000-08:00

We are getting some serious miles on the X58 and liking very much what we see. Intel is surprisingly transparent with their doc. Standards are a great thing. This is getting really fun, really fast.

One of Two ML555s saying "Hello, World"

Implementation Details

2008-12-28T17:14:00.001-08:00

The X58 chipset is rolling out and hopefully it will not be too disruptive to our efforts. I nudged Phil down a path to get his Gen2 training vibe sorted out - and I'm pleased he is making good progress. Our first date of X58 love will not arrive for another few days. In the mean time, I took a swing at trying to get either Linux or WinXP up on the uATX Intel DQ45CB motherboard. The idea is that if I can get a decent uATX platform with at least Gen1 x8 connectivity to an ML555 - we could offer a Space, Weight, and Power (SWaP) FPGA solution with COTS parts. Things seldom go as planned. Everything runs fine in WinXP "safe mode"; but in VGA mode, or with the latest Intel drivers, I fall into a lock up state like image below. Looks like Intel is revving the drivers almost weekly, so I'll just set this aside knowing it is most likely "software". Hopefully we can give it some Ubuntu love too!

Video Wedge on Intel DQ45CB (x45)

Three's a Charm

2008-11-09T09:29:00.000-08:00

Never mind the speed bumps, we have three FPGA nodes coming up fast and furious. Up to seven nodes sit behind a PCIe switch with about 120 nS cut-through latency. ASI may be dead; but PCIe rocks! Learn more about multicomputers here.

Three Happy ML555s - Eager to Communicate

Atomic Rules Live

2008-10-30T10:30:00.000-07:00

Thanks to David and Darlene's tireless work, we launched the Atomic Rules website yesterday. It takes a surprising amount of work to state your manifest value. Like dialing in a strategy though, once it is set, the appropriate tactics are more obvious. The fun continues.

ML555

2008-09-14T12:01:00.001-07:00

I've been putting some miles on the Xilinx ML555 again. This PCIe development card has an LX50T and a surprisingly mature set of off-the-shelf apps. In specific, XAPP859 seems as good as any to quickly get up and running with PCIe.

Five Pushbuttons and Five LEDs

Distraction

2008-09-02T05:36:00.000-07:00

On Labor Day my wife calls me to her studio to point out that her trusty Shuttle SD37P2 PC was making a strange noise. This was remarkable because this box has always been pretty quiet. Fitted with a “green” HDD and a fan-less PCIe GPU, the monitored fans would spin at a low speed, as there was not much power draw. I shut down XP and then popped the case to see the noise was coming from a bearing in one of the two rear fans. It was spinning, but making noise. When I rebooted, there was no BIOS, no video, and no blue LED on the front panel. Grrrr. This machine’s HDD and OS were well tweaked, and although I’m not worried about file-oriented data loss, a great many hours went into building up the OS state over two years. For example, I just installed and activated our copy of Adobe Photoshop on that machine, and I doubt it will be easy to recover that, for example. Never mind all the apps and software versions.

I hold my finger on the front panel power switch to start the PC, the PSU recognizes that, and I see the fans spin. I beep out +5 and +12 on the Molex pins, they are fine. But no video, and no BIOS. I look at the 3.3 tantalums bypassing the DDR DIMMs and there is nothing. Ok, that explains why no BIOS. This motherboard does allow tweaking the DRAM voltage, so that supply is off or dead. I find a bypass cap on the PCIe GPU adjacent to the 3.3 edge supply, and I see 3.5 volts. No 3.3 on the DRAM; hot 3.3 on the PCIe connector.

So I pop out the proprietary form-factor power supply, which Shuttle calls a model PC55, and I can see +5 and +12, but I don’t see any connector pin for +3.3. It doesn’t use the ATX standard. Oddly, the certification label calls out a few amps at 3.3; but provides no wires for that purpose. Suspicious. My guess is that the motherboard makes all the 3.3 it needs from +5 and +12.

I do the power-on/off dance a dozen times in a dozen variations. No evidence of any mechanical intermittent. I try to clear the CMOS by holding the clear-CMOS switch, on the hail-Mary that somehow the BIOS was corrupted on the last orderly shutdown. I have to set this aside now and get back to work. It seems unlikely that the motherboard 3.3 regulator(s) would just die. And it is a drag that I couldn’t find schematics and assembly drawings for the SD37P2 motherboard.

Resting Point

2008-08-06T10:22:00.000-07:00

I've advanced the platform to a functional resting point where I've observed both Altera and Xilinx PCIe TLPs making their merry way to and from (790FX) main memory. I haven't taken the interesting next step of having them interact with each other endpoint-endpoint (and measuring that throughput and latency).

Hardware Components (excluding FPGA/PCIe boards):
HSPC Tech Station Open-Air Case, MSI K9A2 (AMD 790FX chipset) motherboard, AMD Athlon64/5000+ Dual-Core CPU, EVGA/Nvidia GeForce 8800GT (512MB) GPU, 4GB PC8500 System Memory, Enermax EMD625A 625W modular Power Supply, Xigmatek 120mm CPU Cooler, Athena SATA 5-drive bay enclosure, 1x 750 GB System disk, 4x 500 GB RAID disks (2 TB Array), Promise raid controller, Sony DVD/CD R/RW Reader/Burner, Planar 21” 1600x1200 LCD DVI monitor, keyboard, mouse, cables.

Platform Blue in the Tech Station Open Case

Altera, Xilinx, and other Reconfigurable Logic

2008-07-29T03:36:00.000-07:00

With both the Altera and Xilinx PCIe Dev Kits up and running, the task turns to working up repeatable measurement practice for both Latency and Throughput. Initially, we will measure to and from main memory (endpoint/root-complex); later we will measure (endpoint-endpoint). The mainboard chipset (AMD 790FX on this platform) has a lot to do with this - but by comparing various endpoint/root-complex observations, we will be able to deduce the individual contributions.

Platform Blue

2008-07-21T17:50:00.000-07:00

The AMD 790FX chipset supports up to four slots of Gen-2 x16 PCIe. This seems as good a platform as any to demonstrate IP interoperability. I'm bringing up both the Altera and Xilinx PCIe dev kit boards. Out of the box I observed 1,600 MBytes/Sec with the x8 Gen-1.

The Next Great Thing in Reconfigurable Computing

2008-06-23T11:40:00.000-07:00

We live in a time of diverse technological riches and countless opportunities for innovation. From this universe of choice there exists a decidedly smaller set of things actually worth doing; endeavors that create and deliver value through the application of science and math. Reconfigurable computing brings together electrical engineering and computer science to solve problems whose solutions may not be obvious because of difficult or conflicting objectives. Problems where time-to-solution, scalability and correctness enter into the calculus of design as first-class concerns; not afterthoughts or ancillary to more familiar metrics of cost, throughput, latency, area, weight and power. I believe that precisely within this class of problems, a measured attack upon the hackneyed trilemma of quick, cheap and good, is where the next great thing lies.

The FPGA-facing side of the reconfigurable computing story is mature and ripe for the harvest. FPGA vendors have learned to understand and appreciate specialization; their slow-motion annealing of hardcore memory, processor, and I/O setting the stage for further, application-domain specific innovations. Trump cards, partial reconfiguration just one among them, wait to be played.

The rote productization of these technologies is insufficient. A greater value may be brought to market by understanding and besting competitive technology on their weaknesses and limitations. An army of homogeneous cores represents an opportunity, not a threat, for a reconfigurable computing strategy that can specialize without becoming brittle. GPP and GPU vendors who confront their ISA and coherency limitations head-on will be better able to exploit heterogeneity. Software and tool vendors who recognize RTL as platform byte code, an artifact of a compiler and not a design language, will be similarly advantaged.

Time-to-solution, scale, and correctness are first-class concerns. The multicore market is sufficiently immense such that exploiting its limitations presents a great blue sea and extending its reach has no bound. I wish to be among those who will understand, appreciate and exploit this paradigm-shift in reconfigurable computing; quick, cheap and good, the next great thing.

ss 2008-06-23