Well Connected

Validating performance of ADCs and DACs is hard enough for the converter and board vendors. We have those challenges, as well as system level concerns. When you place an converter a few cm from a 100W GPU, how would you think the SFDR would change? Fun stuff.

GPU and FPGA Love

Big DAC Attack

We've been putting some miles on the amazing RF ADCs and DACs that are now available. In particular, we like the Maxim MAX19693, a 4GSPS 12b DAC that is exceptionally well-targeted at our market's needs.

RF Bow-Tie

A Brief History of FMC (VITA-57)

The FPGA Mezzanine Connector (FMC) standard is just starting to become popular. It's said to be "brand new". However work on the concept and specification began in 2005 when FPGA vendors and clients realized that specializing IO for FPGA was a serious challenge. My speculation was that the idea was born in a dialog between David Squires and Craig Lund. They passed the concept along to their respective underlings Sabine Lam and me. On November 16, 2005 over two dozen industry participants came together at the Paramount hotel in Seattle, WA to hash out a standards development roadmap. The team promptly put Malachy Devlin (then CTO and co-founder Nallatech) in the lead role. Throughout 2006 there would be face-face meetings in Monterey, Park City, and Madrid, to work through details not covered in the weekly con-calls. By the end of 2007, the "VITA-57" had become "FMC" (after "XMC", "AMC", etc), and the standard was out for approval. In 2008, VITA placed the documents on their FMC web page. And in 2009 we see the first flush of mezzanines and carriers hitting the market. A lot of work by a broad team to achieve consensus.

Park City, UT

Madrid

Monterey

ISE 11.4 L.68 Looking Great

Like the first winter storm of the season outside our offices, ISE 11.4 L.68 rolled in last night. No issues through our first round of regressions with the OpenCPI oc1001-ml555 baseline. Vendors should follow Xilinx' lead for low-impact, minimally-disruptive minor releases like this.

1500 MHz DAC Pilot Tone

V6 - for real this time

We've seen V6 teasers for months now. But it all became real when Avnet (our distributor) delivered V6-LX240T production silicon on ML605s last week. Fortunately, a rainy November weekend meant full steam ahead. I suppose we were expecting more problems. Essentially, everything works. Nice work, team X! Who's next?

More Boards, Less Risk

This morning we successfully ran the the rplTest regressions on an OpenCPI corei7 reference platform with the Xilinx XUPV5-LX110T board. This bench test involved both passive and active DMA roles, host/fpga and fpga/fpga. The tests included swapping out one of two ML555s for an XUPV5; as well as testing the XUPV5 interacting with the GPP alone.

No Code changes were required to achieve this goal!

For the XUPV5-LX110T, we directed the make target in NGDBUILD to link against a Gen1-x1 NGC core (instead of Gen1-x8 core we use with the ML555), and of course, to use the XUPV5-LX110T UCF. Other than the expected, reduced DMA throughput seen with the Gen1-x1 PCIe link, we observed no functional differences. The bitstream build process for the reference oc1001 application took about 35 minutes.

ML555 and XUPV5

Silicon Valley Scramble

We made a go of Silicon Valley this week, visiting academic, EDA and FPGA luminaries of past, present and future. This expedition found us relentless in replaying our OpenCPI message, with our audience actually comprehending the merits of our work. Reconfigurable Computing (RC) is indeed hard. But the values are real and can be measured against the costs. I'm eager to get back to the lab and playout the assets our hosts desire. Eager so that they can measure them, exploit them, critique them, and thus help steer our future.