Validating PCIe

LeCroy graciously loaned us their exceptional T2-16 PCIe Protocol Analyzer for a few days. This was not nearly enough time to appreciate an instrument that has such deep capabilities. While the T2-16 captures every nook and cranny of the PHY and LINK layers; we remain most-interested in watching what is going on at the Transaction Layer (TL). The T2-16 does this well; but a Ferrari can also take you to the grocery store. Functionally, the most-annoying nit was that the fans on the active interposer and in the chassis itself are screaming loud. And the LAN function didn't work; but USB worked flawlessly. Faced with an intractable, hard-to-understand PCIe issue; this is an instrument we would want by our side.

LeCroy T2-16

FCCM 2011

FCCM 2011 was a success. Good papers, excellent presentations, and a demo night.




Images from FCCM 2011

FCCM 2011 Arrival

Salt Lake City is pretty. The last time I was here, we were we're hashing out the details of the FMC Standard up in Park City. This time it's FCCM. Dinner last night at Fresco was delicious.

FPGA Design Intern Position

Job Title: FPGA Design Intern

Location: Auburn, NH

Stipend: $20/hour

Dates of Position: Flexible

Time Commitment: 3 to 6 months

Reporting To: CTO

Responsibilities: Design, simulation, and test of digital infrastructures and applications. The intern will write, test, and deploy BSV codes that will be contributed to an open-source community. 

Qualifications:

• Bluespec SystemVerilog (BSV) experience (MIT 6.375 or equivalent) (mandatory)
• Experience with FPGA design and tool flows from Verilog sources (mandatory)
• Familiarity with RHEL, C, C++, Tcl, Python, Git and MATLAB 
• Familiarity with OSS projects like www.opencpi.org and www.netfpga.org

Additional Details:

• The intern may work remotely 
• This position is non-ITAR; no clearance or US citizenship is required 
• Atomic Rules builds heterogeneous circuits and systems centered on leading-edge FPGAs. We seek qualified, enthusiastic intern contributors.

Contact greatminds at atomicrules dot com

Ubiquitious 10GbE

Five months after our travels to Dublin we have the NetFPGA-10G "NF10" board lit up and shuttling data across 10GbE and PCIe. There's no looking back, 10GbE is here.

NF10 in Core980 with ML605

It's About Time

We care about time. An ongoing effort is to improve the quality of timestamp available to IP cores inside an FPGA to sub-nanosecond precision. One way forward is to use a stable, but not terribly accurate, on-board XO; and then to discipline it to a highly-accurate, but transient, reference from a GPS. Our approach uses a PI servo that is smart about when to freewheel. No magic. Just math.

Agilent 53230A 20pS Counter/Timer

Narcissism of Small Differences

One of Seth's posts, as it often does, got me thinking.

• emacs vs vi
• VHDL vs Verilog
• AXI vs OCP

The good news is that we care. I was going to add "Functional vs Imperative", then reflected, not such a small difference.