Wednesday, January 10, 2018

The Role of an Advisor

For the past nine years, Atomic Rules has been evolving. Evolving from a single engineer with a singular vision, to an amalgam of a dozen engineers with a team vision. Along the way we've had a lot of help. Help from technology firms like ARM and Xilinx producing the canvas that we draw on. Help from businesses like BittWare who represent our IP products with a worldwide reach. And of course Bluespec Inc, for Bluespec SystemVerilog (BSV), so that our codes would be correct and concise, in a way other Domain Specific Languages can only someday hope to match.
I started Atomic Rules back in 2008 solely offering FPGA design services. We picked up some great clients along the way. A few years in, the idea of producing IP products took hold. Well chosen, customer-driven IP cores would be the future of the company. Not for the squeamish, we knew going in that production IP would require an investment in verification and support significantly above that of just FPGA design services. We got that right.
Atomic Rules now has three full-production IP cores on the market. Available through Xilinx, available through BittWare, and available directly from Atomic Rules. Hooray for us! With such deep and solid investment in products, tens of engineer-years in the making; it’s time for Atomic Rules to pivot and focus even more on sales, customers and product support; and less intensely on speculative R&D.
We will, of course, keep on our existing services clients, continue our relationships with the dozen engineers who make up Atomic Rules, and continue to support and develop new products and technologies. As such, we have a new Chief Operating Officer to do much of the day-to-day triage; and will soon announce a new Engineering Manager. It's all good!
This week I started a full-time position as VP of Research and Development at an exciting startup, Skreens Entertainment, and thus have relinquished my position as CTO of Atomic Rules. Skreens understands that Atomic Rules shall remain a going and growing concern, and I will stay on in an advisory role. And while my daily (and nightly) passion is now making Skreens all that it can be; I'm fortunate that I get to watch the Atomic Rules rocket climb up to orbit as well.

Saturday, June 3, 2017

FPGA with AXI plus GPP with DPDK equals Arkville

And just like that, the passion that has taken so much effort and focus for so long, is launched. The launch this week of Arkville was, for Atomic Rules, a very big deal. By far our most ambitious product to date. We had a lot of help, and really could not have done it alone. The support of The Linux Foundation and the DPDK Community was vital. They ran a must-read terrific interview that really sums it up nicely.

Are we done? No way! Work is already underway for the 17.08 release. Check back here in August.

Tuesday, May 2, 2017

Hoplite Comes of Age

Jan Gray's groundbreaking work on Hoplite has spread far and wide. Besides Jan, nobody has grabbed that baton and run farther with it than Nachiket Kapre. At FCCM2017 earlier this week, we were treated to not one, but two, presentations extending Hoplite in exciting and new directions.

FPGA overlays are a peculiar thing. The proliferation of spatial heterogeneity in reconfigurable computing devices (Trimberger FPL2007, et al) has effectively killed off the promise of a relocatable circuit module.  Overlays fight back, in part, by delivering an abstraction that helps hide the spatial speed bumps.

Kudos to Jan, Nachiket and others who have advanced this work. They are delivering value to the community that may not be fully appreciated until we have our second 25 year retrospective.

Sunday, March 19, 2017

The Road to Arkville

For over a year now, five engineers have applied their passion on the journey of birthing a new product. Arkville is a big deal for Atomic Rules. Coming 18 months after our first product, the UDP Offload Engine, Arkville will be a whole new bag. We're betting that there is significant value at the intersection of two key technologies: DPDK and AXI.

We dont expect this to be an easy journey. Why? Let's take DPDK and AXI one by one.

DPDK is the de facto Linux Kernel Bypass mechanism evolving now for over a decade for use when you need to do useful work on multiple cores without the kernel stack getting in the way. Most DPDK users work with merchant ASIC-based NICs or virtualized NICs. Despite the "Data Plane" in DPDK, not all users see it as just an I/O mechanism. There's more to it.

Also over the past decade, AXI, a proper sub-set of AMBA, has emerged in the FPGA world as a standardized hardware interface and API. If you are building a Green-box fleet of RTL accelerators to go inside your FPGA; you probably want to use AXI for the plumbing. If not, you are probably writing gaskets with a throughput and latency tax.

Atomic Rules understands that both the DPDK GPP software world and the AXI RTL gateware world are two different things. And experts in one are seldom experts in the other. The guiding light for Arkville design has been to take the established DPDK APIs and ABIs and implement a DPDK- and AXI- aware packet conduit between GPP and FPGA. Conceptually abstract, but physically (at product launch in May) to be PCIe. We're excited about all of this, and if you are too, please get in touch. Since you made it this far, here's a hidden link on our site about Arkville in alpha-testing.

Monday, January 16, 2017

Paced Packet Player

We employed our Esopus Creek technology to build a DPDK Paced Packet Player (PPP), shown here inside a Dell R730 server. Four independent 100 GbE ports, line rate, ns accurate, no waiting. Red arrows show the added 12V supply used in this instance. Watch for more Esopus Creek in our upcoming Arkville product offering later this year.

Wednesday, December 2, 2015

Exciting Times

It’s almost 2016. 20nm FPGAs are here and 16 nm are coming. You can buy an inexpensive 128-port OpenFlow switch/router with 10/25/40/50/100 GbE ports. Intel is roaring back into networking with Red Rock Canyon (RRC). Opportunities abound at the endpoints of these commodity communications networks!

An exciting time for Reconfigurable Computing (RC):
  • 20 nm FPGAs are in production
  • 20 nm FPGAs have 25 Gbps+ capable SERDES
  • 25/50/100 GbE technology-enablers
  • Able to serve 10/40 GbE by running SERDES at lower rates
An exciting time for Software Defined Networking (SDN):
  • The P4 language is rapidly evolving
  • Game-Changing Broadcom Tomahawk
  • Game-Changing Intel Red Rock Canyon (RRC)
An exciting time for Atomic Rules:
  • Timing closure at 400 MHz through architecture
  • A UDP/UOE product, first mover for 25 GbE
  • 10/25/100 GbE L2/L3 stacks using production IP

Saturday, April 19, 2014

Dealt a new Deck

We are so excited with the release this week by Xilinx of Vivado 2014.1 . Having been involved since the dark-ages with the underpinnings of this world-class CAD tool for FPGA, we're always eager to see what's new and improved. With almost a dozen 28 nm designs under our belt, we made quick work of porting designs working on platforms like the KC705, VC709, and ZC706 from 2013.4 to 2014.1. We love that we can script in Tcl, or click in the GUI. We like to see both work equally well. We need more time to have hard quantitative evidence, but across the board we are seeing 10~20% placer run time reductions, with no loss of Quality of Results. Not sure where this gain is coming from, but we will measure and find out. This is crazy good. Thanks Xilinx!

Altera is looking to answer with their salvo of Quartus II 14.0 soon, so stay tuned. Altera does have some interesting silicon announced down the pike; and we're happy to bring our RTL to whatever devices our clients are using. Still, from a do-it-all CAD tool perspective, we lament that Quartus lacks a built-in functional simulator like Vivado. Oh well... separation of concerns!

What a world it would be if Xilinx and Altera got out of the CAD tool business and just focused on world-class FPGA silicon, leaving the EDA tools to the EDA tool vendors. Or to the open source community! It's nice to dream. Still, with tool suites like Vivado that build in aspects like IP Integrator, and IP Packager, we're glad (for now) that the FPGA vendors are in the EDA game.