Wednesday, March 7, 2012

MathWorks MATLAB R2012A

We are excited about MathWorks release of MATLAB R2012A and the rest of the product suite. There were no unexpected surprises and quite a few new features. Our clients are thrilled we're on the leading edge and we are proud to be a MathWorks Connections Partner.

Sunday, February 26, 2012

Instead of "No", explore "How"

Steve Trimberger explained to me a client engagement technique which I appreciated. Our discussion stemmed from a mutual desire as engineers to be honest to our science, while at the same time allowing our businesses to thrive.

When a potential client volleys a challenge that strays from your centerline, instead of a tacit “No”, offer up “How”. There is a spectrum of how. Perhaps how is a development effort unaligned with your current world view? Perhaps how is a story that you tell with some embarrassment?

This is consistent with the Happy Mistakes meme in that allows you extract information from a scenario that would otherwise be a dead end. It is especially useful if, in telling the story, you do measure some embarrassment, and you now have voice-of-the-customer feedback to guide you forward. Of course, "How" may also lead you down a path that turns a "No" to a "Yes".

Sunday, January 29, 2012

KC705 Supported

With the release this month of ISE 13.4, we have added the Xilinx KC705 to the list of supported OpenCPI FPGA platforms. We adapted the new AXI-centric Gen2 x4/x8 PCIe endpoint to our uNoC without much drama. Inbound (RX) straddled packets were an interesting twist. Kudos to the Xilinx team for producing such a clean and easy-to-use evaluation kit and help jumpstart our community adoption of 28nm FPGAs in practice. The KC705 is fitted with a Xilinx Kintex-7 XC7K325T device.

KC705 at Atomic Rules

Thursday, December 1, 2011

North American FPGA Conferences

Atomic Rules is pleased to be a sponsor of two FPGA conferences in 2012:
Please click through the links above to get the details on the call-for-papers and other participation.
Additionally, you can check our News and Events page to see what else is in the works.


Shep and Oskar at Demo night, FCCM-2005 (Napa)

Monday, November 28, 2011

SIGINT bliss and the MDO4104

Regrettably we will part today with the Tektronix MDO4104-3 mixed-domain scope which we have been renting for two months. This is has been a superb instrument to use to line up RF and baseband signals. We hope to see this tool on our bench again soon.

Tektronix MDO4104-3 at Atomic Rules

Wednesday, August 31, 2011

FPGA Cross-Vendor Interoperability

A short video showing OpenCPI transport messages between Altera and Xilinx FPGA platforms.

Tuesday, August 16, 2011

Pure PCIe

The PCIe specification does a splendid job of describing how Transaction Level Packets (TLPs) are encoded. The specification precisely defines an interface without dictating an implementation. It’s a terrific concept.

FPGA and ASIC IP vendors, when providing said TLP interfaces to their users, make implementation choices that are specific to their own technological and marketing whims. These choices run the gamut from reasonable to ridiculous: Big-endian vs. Little-endian? Streaming or not? Header vs. Payload? Strict or Uncertain flow-control.? Packing “bubbles” and straddled packets? My goodness: All of these to alter of protocol gods that have little to do with PCIe TLPs themsleves!

Faced with the challenge of achieving interoperability with and between any of these PCIe endpoints; out of necessity, we followed a simple process. We designed a Pure PCIe intermediate “platform” that used nothing other than the “pure” PCIe specification for its definition. In this way, the work involved with adapting any PCIe device (now or future) has one overarching goal: Adapt the variable implementation to the fixed, pure PCIe interface.

The utility of this simple approach is that interconverting between different implementations is now just a matter of hooking them to the other side of the pure PCIe interface. We get multiplicative gains in interoperability for a linear effort in design cost. And we get the verification leverage of only having to compare one unknown (the new protocol) to one bulletproof interface (the PCIe TLP spec) at a time.

The lesson here is that there are indeed clever tactics one can take to embrace the reality that new protocols (some brilliant, some defective) will continue to assault us as they are invented. By recognizing stable, more cardinal interfaces (such as PCIe TLPs), we can adopt them all, without as much drama and cost.