Implementation Details

The X58 chipset is rolling out and hopefully it will not be too disruptive to our efforts. I nudged Phil down a path to get his Gen2 training vibe sorted out - and I'm pleased he is making good progress. Our first date of X58 love will not arrive for another few days. In the mean time, I took a swing at trying to get either Linux or WinXP up on the uATX Intel DQ45CB motherboard. The idea is that if I can get a decent uATX platform with at least Gen1 x8 connectivity to an ML555 - we could offer a Space, Weight, and Power (SWaP) FPGA solution with COTS parts. Things seldom go as planned. Everything runs fine in WinXP "safe mode"; but in VGA mode, or with the latest Intel drivers, I fall into a lock up state like image below. Looks like Intel is revving the drivers almost weekly, so I'll just set this aside knowing it is most likely "software". Hopefully we can give it some Ubuntu love too!

Video Wedge on Intel DQ45CB (x45)

Three's a Charm

Never mind the speed bumps, we have three FPGA nodes coming up fast and furious. Up to seven nodes sit behind a PCIe switch with about 120 nS cut-through latency. ASI may be dead; but PCIe rocks! Learn more about multicomputers here.

Three Happy ML555s - Eager to Communicate

Atomic Rules Live

Thanks to David and Darlene's tireless work, we launched the Atomic Rules website yesterday. It takes a surprising amount of work to state your manifest value. Like dialing in a strategy though, once it is set, the appropriate tactics are more obvious. The fun continues.

ML555

I've been putting some miles on the Xilinx ML555 again. This PCIe development card has an LX50T and a surprisingly mature set of off-the-shelf apps. In specific, XAPP859 seems as good as any to quickly get up and running with PCIe.

Five Pushbuttons and Five LEDs

Distraction

On Labor Day my wife calls me to her studio to point out that her trusty Shuttle SD37P2 PC was making a strange noise. This was remarkable because this box has always been pretty quiet. Fitted with a “green” HDD and a fan-less PCIe GPU, the monitored fans would spin at a low speed, as there was not much power draw. I shut down XP and then popped the case to see the noise was coming from a bearing in one of the two rear fans. It was spinning, but making noise. When I rebooted, there was no BIOS, no video, and no blue LED on the front panel. Grrrr. This machine’s HDD and OS were well tweaked, and although I’m not worried about file-oriented data loss, a great many hours went into building up the OS state over two years. For example, I just installed and activated our copy of Adobe Photoshop on that machine, and I doubt it will be easy to recover that, for example. Never mind all the apps and software versions.

I hold my finger on the front panel power switch to start the PC, the PSU recognizes that, and I see the fans spin. I beep out +5 and +12 on the Molex pins, they are fine. But no video, and no BIOS. I look at the 3.3 tantalums bypassing the DDR DIMMs and there is nothing. Ok, that explains why no BIOS. This motherboard does allow tweaking the DRAM voltage, so that supply is off or dead. I find a bypass cap on the PCIe GPU adjacent to the 3.3 edge supply, and I see 3.5 volts. No 3.3 on the DRAM; hot 3.3 on the PCIe connector.

So I pop out the proprietary form-factor power supply, which Shuttle calls a model PC55, and I can see +5 and +12, but I don’t see any connector pin for +3.3. It doesn’t use the ATX standard. Oddly, the certification label calls out a few amps at 3.3; but provides no wires for that purpose. Suspicious. My guess is that the motherboard makes all the 3.3 it needs from +5 and +12.

I do the power-on/off dance a dozen times in a dozen variations. No evidence of any mechanical intermittent. I try to clear the CMOS by holding the clear-CMOS switch, on the hail-Mary that somehow the BIOS was corrupted on the last orderly shutdown. I have to set this aside now and get back to work. It seems unlikely that the motherboard 3.3 regulator(s) would just die. And it is a drag that I couldn’t find schematics and assembly drawings for the SD37P2 motherboard.

Resting Point

I've advanced the platform to a functional resting point where I've observed both Altera and Xilinx PCIe TLPs making their merry way to and from (790FX) main memory. I haven't taken the interesting next step of having them interact with each other endpoint-endpoint (and measuring that throughput and latency).

Hardware Components (excluding FPGA/PCIe boards):
HSPC Tech Station Open-Air Case, MSI K9A2 (AMD 790FX chipset) motherboard, AMD Athlon64/5000+ Dual-Core CPU, EVGA/Nvidia GeForce 8800GT (512MB) GPU, 4GB PC8500 System Memory, Enermax EMD625A 625W modular Power Supply, Xigmatek 120mm CPU Cooler, Athena SATA 5-drive bay enclosure, 1x 750 GB System disk, 4x 500 GB RAID disks (2 TB Array), Promise raid controller, Sony DVD/CD R/RW Reader/Burner, Planar 21” 1600x1200 LCD DVI monitor, keyboard, mouse, cables.

Platform Blue in the Tech Station Open Case

Altera, Xilinx, and other Reconfigurable Logic

With both the Altera and Xilinx PCIe Dev Kits up and running, the task turns to working up repeatable measurement practice for both Latency and Throughput. Initially, we will measure to and from main memory (endpoint/root-complex); later we will measure (endpoint-endpoint). The mainboard chipset (AMD 790FX on this platform) has a lot to do with this - but by comparing various endpoint/root-complex observations, we will be able to deduce the individual contributions.

Platform Blue

The AMD 790FX chipset supports up to four slots of Gen-2 x16 PCIe. This seems as good a platform as any to demonstrate IP interoperability. I'm bringing up both the Altera and Xilinx PCIe dev kit boards. Out of the box I observed 1,600 MBytes/Sec with the x8 Gen-1.

The Next Great Thing in Reconfigurable Computing

We live in a time of diverse technological riches and countless opportunities for innovation. From this universe of choice there exists a decidedly smaller set of things actually worth doing; endeavors that create and deliver value through the application of science and math. Reconfigurable computing brings together electrical engineering and computer science to solve problems whose solutions may not be obvious because of difficult or conflicting objectives. Problems where time-to-solution, scalability and correctness enter into the calculus of design as first-class concerns; not afterthoughts or ancillary to more familiar metrics of cost, throughput, latency, area, weight and power. I believe that precisely within this class of problems, a measured attack upon the hackneyed trilemma of quick, cheap and good, is where the next great thing lies.

The FPGA-facing side of the reconfigurable computing story is mature and ripe for the harvest. FPGA vendors have learned to understand and appreciate specialization; their slow-motion annealing of hardcore memory, processor, and I/O setting the stage for further, application-domain specific innovations. Trump cards, partial reconfiguration just one among them, wait to be played.

The rote productization of these technologies is insufficient. A greater value may be brought to market by understanding and besting competitive technology on their weaknesses and limitations. An army of homogeneous cores represents an opportunity, not a threat, for a reconfigurable computing strategy that can specialize without becoming brittle. GPP and GPU vendors who confront their ISA and coherency limitations head-on will be better able to exploit heterogeneity. Software and tool vendors who recognize RTL as platform byte code, an artifact of a compiler and not a design language, will be similarly advantaged.

Time-to-solution, scale, and correctness are first-class concerns. The multicore market is sufficiently immense such that exploiting its limitations presents a great blue sea and extending its reach has no bound. I wish to be among those who will understand, appreciate and exploit this paradigm-shift in reconfigurable computing; quick, cheap and good, the next great thing.

ss 2008-06-23