Xilinx shipped Vivado 2013.1 last week. If the engineering design and verification community needed any validation that "FPGA CAD Tools are closing ground on their ASIC centric brethren", Vivado is an excellent example. We see so much runway and room to grow here that we've been making proactive investments around nascent aspects of Vivado, such as IP Integrator (IPI). Our efforts in this regard were mentioned in this press release.
While most of our clients are in the heart of design cycles with 28nm silicon; we are also supporting a user base with legacy silicon, particularly Xilinx 6-series, such as the olde-timey, four year old, ML605 platform. To this end, ISE has bumped from 14.4 to 14.5. We are progressing through our regression tests for OpenCPI and others without drama.