Altera, Xilinx, and other Reconfigurable Logic

With both the Altera and Xilinx PCIe Dev Kits up and running, the task turns to working up repeatable measurement practice for both Latency and Throughput. Initially, we will measure to and from main memory (endpoint/root-complex); later we will measure (endpoint-endpoint). The mainboard chipset (AMD 790FX on this platform) has a lot to do with this - but by comparing various endpoint/root-complex observations, we will be able to deduce the individual contributions.

Platform Blue

The AMD 790FX chipset supports up to four slots of Gen-2 x16 PCIe. This seems as good a platform as any to demonstrate IP interoperability. I'm bringing up both the Altera and Xilinx PCIe dev kit boards. Out of the box I observed 1,600 MBytes/Sec with the x8 Gen-1.