More Boards, Less Risk

This morning we successfully ran the the rplTest regressions on an OpenCPI corei7 reference platform with the Xilinx XUPV5-LX110T board. This bench test involved both passive and active DMA roles, host/fpga and fpga/fpga. The tests included swapping out one of two ML555s for an XUPV5; as well as testing the XUPV5 interacting with the GPP alone.

No Code changes were required to achieve this goal!

For the XUPV5-LX110T, we directed the make target in NGDBUILD to link against a Gen1-x1 NGC core (instead of Gen1-x8 core we use with the ML555), and of course, to use the XUPV5-LX110T UCF. Other than the expected, reduced DMA throughput seen with the Gen1-x1 PCIe link, we observed no functional differences. The bitstream build process for the reference oc1001 application took about 35 minutes.

ML555 and XUPV5