Protégé Disassociation Disorder

I dislike the aphorism “all good things must come to pass.” Do they? Really?! Sixteen weeks seemed like it would be a long time when we started; but it passed in a milli-moment. The lab is quieter (I don’t talk to myself much), and even though the sun is shining brightly on the future, there is unquestionably a sadness in such things. Selected solution vector: Go forward and be awesome with the tools and talent we can muster. I like that.
Hit up a recommendation of our erstwhile intern over at LinkedIn.

Christina at work, Fall 2012

Productivity Multiplied

"Productivity. Multiplied." that's the slogan for Xilinx's Vivado tool suite. I wonder if the marketing folk understand that actual multiplication of productivity stems not from the tools; but from those who design, train, support and ultimately use them? We love Vivado, warts and all. When you consider the depth and sophistication of the offering, it is possibly one of the best digital design CAD tool values ever. That it's married up with 28nm series-7 silicon that has been evolving for over a quarter a century doesn't hurt. Add the standardization of AXI interfaces, as opposed to the wild-west with every IP for itself; and the situation looks good.
Mike with Christina, holding the one series-7 platform we have spent almost no time with!

Xilinx DocNav in RHEL6

With a little more effort, we got Xilinx DocNav up and running with RHEL6.3. This includes multi-tabbed browsing with Acrobat Reader when clicking multiple documents in DocNav.

If you haven't used DocNav, you should try it. Quick access to the latest versions of almost all Xilinx doc.

One insight here is that neither Red Hat or Xilinx can redistribute Acrobat, we're told. So we found and tried a blog post that makes it easy to do a clean install of Acrobat Reader from the Adobe repos.

The RHEL6.3 desktop is starting to be a nice place to code.

Xilinx Vivado RHEL6 and USB JTAG

Xilinx advertises that RHEL6 64b is a supported operating system for their Vivado tools suite. We love Vivado, but join the rest of the world in lamenting that support for the USB JTAG drivers under Linux in general and RHEL6 64b in specific is rough. We strongly suggest that if you too are having these issues, you file a webcase with Xilinx, and work with them to resolve your particular problem.

Sometimes you have to go a little outside the box to get something done; and that is what we just went through last night on our own, in order to get USB JTAG connectivity with Vivado 2012.3 and RHEL6 64b. First, we followed the well-known workaround that our Stanford friends list here, the third question down.

That didn't quite do the trick as we were still seeing 03fd:00d and not 03fd:0008 in response to lsusb. This is because /sbin/fxload does not come with RHEL6. I struggled in building it from sources and eventually gave up by finding an RPM pointed to here.

Cracking that nut got us to 03fd:0008 with lsusb and made Vivado (and Impact) functional.

At least one annoying USB related hurdle remains. The newer on-card USB adapters on the VC707 and KC705 do not work this way: you have to use an olde-timey USB/JTAG ribbon cable dongle and plug to the JTAG header. Interestingly, the older ML605 does work. And all the boards talk just fine with Win7 64b.

As others observing these Linux USB/JTAG issues with Vivado clearly and calmly file well-written webcases, Xilinx will have the data they need to make USB/JTAG as awesome and functional as the rest of the Vivado suite.

Dubstep Productivity

This may sound crazy, but it's true. We've been playing classical music in the lab at low levels for about four years as an acoustic cushion over the nosier instruments, computers, and engineers. Recently, we changed our listening to a Dubstep vibe: specifically the Dub Step Beyond channel from SomaFM. Guess what? A quantitative improvement in productivity; plus we are happy! If this works in your lab too, we suggest you donate to SomaFM, as we did for this great mindset.
This is a good sign!

Joy of Collaborating

Our intern came in to work today, a Sunday, because she wanted to. I wanted to work too; not the whole day, just a few hours to get some things done. It turns out that in a few minutes of collaboration we found a defect in our code that had been overlooked. The code passed our tests, performed its function, only it did so in a non-compliant way. Collaboration in engineering is vital for risk reduction. Collaboration with a bright, knowledge-thirsty grad student is much better; it's fast-moving, rewarding and fun.

Vivado 2012.2 / ISE 14.2

Xilinx released Vivado 2012.2 / ISE 14.2 today. Aside from advancing some of the 7-series goodness we've been waiting for with the KC705, we were thrilled that Xilinx fixed issues we were having with PlanAhead when targeting the long-in-the-tooth Spartan 3-DSP devices used in the popular Ettus radios. Nice: We love PlanAhead and we're glad it works great with S3-DSP.

FCCM-2012 Toronto

I arrived at FCCM-2012 Toronto yesterday and had a nice walk around the UT campus. Excellent Indian diner last night at Banjara with Microsoft Research, UPenn, and Imperial all chiming in. Looking forward to the Sunday workshop today, and the rest of the conference in general. These guys are changing the world while we do our small part translating bits of spectrum up and down, hopefully without getting too much in anyone's way.

MathWorks MATLAB R2012A

We are excited about MathWorks release of MATLAB R2012A and the rest of the product suite. There were no unexpected surprises and quite a few new features. Our clients are thrilled we're on the leading edge and we are proud to be a MathWorks Connections Partner.

Instead of "No", explore "How"

Steve Trimberger explained to me a client engagement technique which I appreciated. Our discussion stemmed from a mutual desire as engineers to be honest to our science, while at the same time allowing our businesses to thrive.

When a potential client volleys a challenge that strays from your centerline, instead of a tacit “No”, offer up “How”. There is a spectrum of how. Perhaps how is a development effort unaligned with your current world view? Perhaps how is a story that you tell with some embarrassment?

This is consistent with the Happy Mistakes meme in that allows you extract information from a scenario that would otherwise be a dead end. It is especially useful if, in telling the story, you do measure some embarrassment, and you now have voice-of-the-customer feedback to guide you forward. Of course, "How" may also lead you down a path that turns a "No" to a "Yes".

KC705 Supported

With the release this month of ISE 13.4, we have added the Xilinx KC705 to the list of supported OpenCPI FPGA platforms. We adapted the new AXI-centric Gen2 x4/x8 PCIe endpoint to our uNoC without much drama. Inbound (RX) straddled packets were an interesting twist. Kudos to the Xilinx team for producing such a clean and easy-to-use evaluation kit and help jumpstart our community adoption of 28nm FPGAs in practice. The KC705 is fitted with a Xilinx Kintex-7 XC7K325T device.

KC705 at Atomic Rules