We got our hands on a real ML605 with ES1 silicon for a few days. Real harmony of tools, silicon, and etch. Have to give the loaner back tomorrow. But production boards are around the corner. Sweet 40nm Fun
By all accounts, FPL 2009 in Prague was a success. We were especially excited about the interest in Open-Source for FPGA; both the opportunities and challenges. Fully expect reverberations in this regard to influence FPGA 2010 and FCCM 2010. High Technology Steve, Vaughn and Kati at Mustek
With the first drop of code out on the OpenCPI website we are doing some cleanup and feature-creep. We decided that the control plane should be able to swallow anything thrown at it; not just well formed 32b and 64b transfers. An OpenCPI FPGA Hierarchy
We've been having fun with beta versions of the backend tools from our FPGA vendors. Yesterday, ISE 11.2 L.46 went live, bringing V6/S6 builds into the non-NDA public eye. From our V5 ML555 viewpoint, things look great indeed.
We moved closer to our goal of providing a vendor- and substrate-agnostic application container as the OpenCPI website went live last week. Much more on this in the months ahead. OpenCPI Development - Spring 2009
We witnessed a demo of functional Xilinx V6 Silicon yesterday on their ML605 evaluation board. The Serdes was functional and operating at the 5 GHz needed for Gen2 PCIe. The two connectors on top are the VITA-57/FMC connectors. ML-605 V6 Eval Board