Altera, Xilinx, and other Reconfigurable Logic

With both the Altera and Xilinx PCIe Dev Kits up and running, the task turns to working up repeatable measurement practice for both Latency and Throughput. Initially, we will measure to and from main memory (endpoint/root-complex); later we will measure (endpoint-endpoint). The mainboard chipset (AMD 790FX on this platform) has a lot to do with this - but by comparing various endpoint/root-complex observations, we will be able to deduce the individual contributions.

Platform Blue

The AMD 790FX chipset supports up to four slots of Gen-2 x16 PCIe. This seems as good a platform as any to demonstrate IP interoperability. I'm bringing up both the Altera and Xilinx PCIe dev kit boards. Out of the box I observed 1,600 MBytes/Sec with the x8 Gen-1.

The Next Great Thing in Reconfigurable Computing

We live in a time of diverse technological riches and countless opportunities for innovation. From this universe of choice there exists a decidedly smaller set of things actually worth doing; endeavors that create and deliver value through the application of science and math. Reconfigurable computing brings together electrical engineering and computer science to solve problems whose solutions may not be obvious because of difficult or conflicting objectives. Problems where time-to-solution, scalability and correctness enter into the calculus of design as first-class concerns; not afterthoughts or ancillary to more familiar metrics of cost, throughput, latency, area, weight and power. I believe that precisely within this class of problems, a measured attack upon the hackneyed trilemma of quick, cheap and good, is where the next great thing lies.

The FPGA-facing side of the reconfigurable computing story is mature and ripe for the harvest. FPGA vendors have learned to understand and appreciate specialization; their slow-motion annealing of hardcore memory, processor, and I/O setting the stage for further, application-domain specific innovations. Trump cards, partial reconfiguration just one among them, wait to be played.

The rote productization of these technologies is insufficient. A greater value may be brought to market by understanding and besting competitive technology on their weaknesses and limitations. An army of homogeneous cores represents an opportunity, not a threat, for a reconfigurable computing strategy that can specialize without becoming brittle. GPP and GPU vendors who confront their ISA and coherency limitations head-on will be better able to exploit heterogeneity. Software and tool vendors who recognize RTL as platform byte code, an artifact of a compiler and not a design language, will be similarly advantaged.

Time-to-solution, scale, and correctness are first-class concerns. The multicore market is sufficiently immense such that exploiting its limitations presents a great blue sea and extending its reach has no bound. I wish to be among those who will understand, appreciate and exploit this paradigm-shift in reconfigurable computing; quick, cheap and good, the next great thing.

ss 2008-06-23