We witnessed a demo of functional Xilinx V6 Silicon yesterday on their ML605 evaluation board. The Serdes was functional and operating at the 5 GHz needed for Gen2 PCIe. The two connectors on top are the VITA-57/FMC connectors. ML-605 V6 Eval Board
Hi, i am an ASIC engineer from China. I got the ML605 photo from your blog.Can i ask you the issues about ML605?
1>what interface does the ML605 include? SFP,SATA,Nand flash,etc? 2>it seems that the board is PCIEx8 lane. does it support PCIE2.0? 3>any more docs about ML605? 4>does V6 GTP support exceed 10G line rate? and it am good at PCIE/SATA/Ethernet/ARM design.
1 comment:
Hi, i am an ASIC engineer from China. I got the ML605 photo from your blog.Can i ask you the issues about ML605?
1>what interface does the ML605 include?
SFP,SATA,Nand flash,etc?
2>it seems that the board is PCIEx8 lane. does it support PCIE2.0?
3>any more docs about ML605?
4>does V6 GTP support exceed 10G line rate?
and it am good at PCIE/SATA/Ethernet/ARM design.
Regards
arcdoos@yahoo.com
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